1. Field of the Invention
The present invention relates to a display and a display panel thereof, and more particularly to a liquid crystal display and a display panel thereof capable of adjusting a common voltage automatically.
2. Description of Related Art
In recent years, liquid crystal displays (LCDS) have been widely adopted and have replaced the conventional cathode ray tube (CRT) displays. Currently, the LCDs have become one of the mainstream products in the market of displays. With the progress of the semiconductor technology, LCD panels have the advantages of low power consumption, slimness and compactness, high resolution, high color saturation, long life time, and so on. Therefore, the LCD panels have been extensively applied in electronic products closely related to daily life, including liquid crystal screens of computers and LCD TVs.
FIG. 1 illustrates a pixel configuration 100 of a conventional thin film transistor liquid crystal display (TFT-LCD). Please refer to FIG. 1. The pixel configuration 100 includes a TFT 101, a liquid crystal capacitance CLC, a storage capacitance Cs, a common electrode CE, and a parasitic capacitance Cgd. The electrical connection of the pixel configuration 100 disclosed in FIG. 1 clearly indicates a Cs-on-common design. FIG. 2 illustrates another pixel configuration 200 of the conventional TFT-LCD. Please refer to FIGS. 1 and 2 together. The main difference between the pixel configurations 100 and 200 lies in that the pixel configuration 200 is of a Cs-on-gate design.
When the voltage level of a scan voltage (VG) outputted by a gate driver (not shown) rapidly declines from a high voltage level (VGH) to a low voltage level (VGL) and the TFT 101 is then switched off, a coupling effect is induced by the parasitic capacitance Cgd no matter which pixel configuration is adopted. Thereby, the voltage in a drain d of the TFT 101 is simultaneously dropped by a voltage level (ΔVD), which can be represented by the following equation 1.
                              Δ          ⁢                                          ⁢                      V            D                          =                                            C              gd                                                      C                gd                            +                              C                s                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            GP                                              Equation        ⁢                                  ⁢                  (          1          )                    
In equation 1, ΔVGP is obtained by subtracting the low voltage level (VGL) from the high voltage level (VGH) i.e. ΔVGP=VGH−VGL. The varying voltage level (ΔVD) is called a feed-through voltage of the scan voltage, and the value of said feed-through voltage is not a constant.
Due to physical characteristics of liquid crystal molecules, however, the value of the liquid crystal capacitance CLC varies according to different gray-level voltages. Hence, every pixels with different gray levels has different feed-through voltages (ΔVD) of the scan voltage. In addition, it is well known that each of the scan lines in the display panel (not shown) includes a parasitic capacitance and a parasitic resistance on a scan line. Accordingly, said ΔVGP is affected by the parasitic capacitance and the parasitic resistance on the scan line, thus resulting in a so-called RC delay. Thereby, the farther the distance between an input terminal of the scan voltage and its corresponding pixel is, the smaller the value of ΔVGP becomes. Besides, due to various RC delays on each of the scan lines in the display panel, the feed-through voltages (ΔVD) of pixels in the same column in the display panel may be different.
As described above, both factors resulting in different feed-through voltages (ΔVD) of the scan voltages lead to an increase in flicker noises of the display panel, and thereby images displayed by the TFT-LCD flicker. To resolve said problems, relevant solutions disclosed in the related art have been correspondingly developed, including:
1. Adjusting the common voltage Vcom supplied to the pixels in the display panel based on the value of the feed-through voltage (ΔVD) of the scan voltage.
2. Adopting a technology of driving a three-level or a four-level scan voltage.
Said solution 1 is adapted to the pixel configuration 100 (Cs on common) and to the pixel configuration 200 (Cs on gate), which is implemented by observing and adjusting the common voltage Vcom supplied to the pixels in the display panel through optical measurements, such that the flicker noises in the middle of the display panel can be minimized. Then, after the adjusted common voltage is set, a corrected gamma voltage outside a source driver is fine tuned to eliminate the shift of the feed-through voltage (ΔVD) Of the scan voltage. Said shift is caused by variation in the value of the liquid crystal capacitance CLC due to different gray-level voltages. It should be mentioned that the problem of the flicker noises at both sides of the display panel is not completely overcome even though said solution 1 minimizes the flicker noises in the middle of the display panel.
FIG. 3 is a diagram of a simulation waveform depicting said solution 1. Please refer to FIGS. 1˜3 together. As shown in FIG. 3, the diagram of the simulation waveform includes a waveform of the scan voltage VG, of the data voltage Vs (the data voltage supplied by the source driver and received by the source s of the TFT 101), of the display voltage VD (the display voltage of the drain d of the TFT 101), and of the common voltage Vcom. Here, the coupling effect induced by said parasitic capacitance Cgd generates the feed-through voltage ΔVD of the scan voltage, which can be learned from the waveform of the display voltage VD.
In view of the foregoing, complicated manual measurement is required when the solution 1 is adopted to resolve the problem of the feed-through voltage (ΔVD) of the scan voltage, so as to obtain the best common voltage Vcom supplied to the pixel in the display panel. Moreover, each display panel has different characteristics, and therefore said best common voltage Vcom and the fine-tuned corrected gamma voltage outside the source driver may not be applicable to all display panels.
Furthermore, said solution 2 can merely be used in the pixel configuration 200 (Cs on gate) disclosed hereinbefore. FIG. 4 is a diagram of a simulation waveform depicting said solution 2 which adopts a technology of driving a three-level scan voltage. Please refer to FIGS. 2 and 4 together. According to said solution 2, as the scan voltage VG of the previous scan line Gm-1 is set at a low voltage level VGL1(m-1), and the feed-through voltage ΔVD of the scan voltage VG of the scan line Gm occurs, the scan voltage of the previous scan line Gm-1 at the low voltage level VGL1(m-1) is raised by a voltage level Vp to a low voltage level VGL2(m-1). Through said increase in the voltage level and the voltage coupling effects of the storage capacitance Cs and of the parasitic capacitance Cgd, the shift of the feed-through voltage ΔVD of the scan voltage VG of the scan line Gm is compensated. Theoretically, the voltage level Vp described in said solution 2 can be calculated through the following two equations:
                              Δ          ⁢                                          ⁢                      V            D                          =                                            C              gd                                                      C                gd                            +                              C                s                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            GP                                              Equation        ⁢                                  ⁢                  (          2          )                                                  Δ          ⁢                                          ⁢                      V            D                          =                                            C              s                                                      C                gd                            +                              C                s                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            GP                                              Equation        ⁢                                  ⁢                  (          3          )                    
However, if a technology of driving a multi-level e.g. a three- or a four-level scan voltage is intended to be developed according to said solution 2, it is obvious that said development complicates the design of the gate driver. Besides, given that the voltage level Vp cannot be accurately calculated by the gate driver, the feed-through voltage ΔVD of the scan voltage VG of the scan line Gm may be insufficiently or excessively compensated, which results in uncertainties in terms of design and measurement. Moreover, it is required for said solution 2 to be implemented in conjunction with the fine-tuned corrected gamma voltage outside the source driver so as to compensate the shift of the feed-through voltage of the scan voltage. The shift is caused by variation in the value of the liquid crystal capacitance CLC due to different gray-level voltages.